1. Field of the Invention
The present invention relates to semiconductor fabrication and more particularly, to a structure and method for forming a vertical MOSFET over a buried bit line conductor with stacked capacitors formed above the surface of the silicon.
2. Background of the Invention
Present trends in DRAM technology are constantly driving towards reduction in minimum feature size and more compact cell layouts. As a result of the need for ever increasing array densities, the scalability of contemporary planar MOSFET cells using trench storage capacitors for feature sizes equal to 150 nm and smaller is facing fundamental concerns. The main concern with the scalability of the cell MOSFET is the increased p-well doping concentration needed to meet off-current objectives. It is known in the art that increased array well doping concentration may result in a marked increase in array junction leakage, which degrades retention time. The problems of scalability related to the cell MOSFET, by itself, is driving the paradigm shift towards vertical MOSFET access transistors in the array.
As far as storage capacitors are concerned, as ground rules are reduced the amount of capacitance available from deep trench storage capacitors decreases. This is a result of limitations on the scalability of the thickness of the node dielectric, limitations on the etch depth of the deep trench, and because of the reduction of capacitance area that occurs with ground rule reduction (scaling) and more dense cell layouts. RIE lag effect caused by the smaller storage trench openings makes etching adequately deep trenches difficult. Filling of this extremely high aspect ratio, for example, aspect ratios greater than 50:1, presents major difficulties. Furthermore the higher aspect ratios associated with aggressively scaled deep trench capacitors results in increased series resistance, which, in turn, results in greatly decreased signal development within a given time window. Barring any significant developments regarding higher dielectric constant node insulators and trench fill materials having lower resistivity, it is predicted that trench capacitor storage elements may not be practical beyond the 120 nm generation. Therefore, the long-term (100 nm and beyond) prognosis for the favored DRAM storage element appears to be stacked capacitors (STC). Still, significant improvements concerning the leakage and reliability of high dielectric materials (i.e. BTSO) for STC cells must occur before widespread manufacturing is likely. However, because of the popularity of STC DRAM, extensive industry wide resources are being directed to solve the problems associated with BSTO and other high dielectric materials.
Integration of vertical access MOSFETs and stacked capacitors is a challenging task and has not yet been adopted by the industry. As commonly practiced by DRAM manufacturers, word lines, bit lines and stacked capacitors all reside on or above the silicon surface. Such an arrangement of these cell elements with a vertical access transistor would apparently complicate forming the connections with the access transistor and would also apparently occupy more silicon real estate than deep trench capacitor DRAM cells with vertical access MOSFETS. Only a limited amount of art exists for STC cells with access transistors having some portion of the channel oriented vertically. The use of vertically oriented channels seeks to decouple the channel length of the cell access MOSFET from the minimum lithographic feature size.
Although some existing DRAM cells employing vertical MOSFETs offer very significant scalability advantages over conventional planar design practiced today, there is still a great deal of room for improvement. For example, for cells using vertical MOSFETs and trench storage capacitors, a single bit line contact is commonly used to access a pair of bits; the pair of bits share a common silicon active area. In this type of cell dynamic coupling between the two back to back vertical MOSFETs results in charge pumping effects and loss of signal. Modeling has shown that electrons pumped into the P-well from a collapsing channel inversion layer of one cell may be collected by the storage node of the adjacent cell sharing the same active area. These coupling effects are accentuated as dimensions are scaled down. Modeling projections indicate that scalability to 100 nm and below may be problematic because of dynamic charge loss due to coupling between adjacent cells.
Thus, there is a need for a DRAM cell containing vertical access transistors and stacked capacitor storage elements. It is desired that the dynamic coupling effect between adjacent vertical MOSFETs be reduced or eliminated to extend scalability below 100 nm feature size.
The present invention provides a method of forming a vertical transistor. A pad layer is formed over a semiconductor substrate. A trough is formed through the pad layer and in the semiconductor substrate. A bit line is formed buried in the trough. The bit line is enclosed by a dielectric material. A strap is formed extending through the dielectric material to connect the bit line to the semiconductor substrate. The trough is filled above the bit line with a conductor. The conductor is cut along its longitudinal axis such that the conductor remains on one side of the trough. Wordline troughs are formed, substantially orthogonal to the bit line, above the semiconductor substrate. A portion of the conductor is removed under the wordline trough to separate the conductor into separate gate conductors. Wordlines are formed in the wordline trough connected to the separate gate conductors.
Additionally, the present invention provides a method of forming a semiconductor device. A pad layer is formed over a semiconductor substrate. A hard mask is formed on the pad layer. A nitride layer is formed on the hard mask. A trough is formed into the semiconductor substrate. A bit line is formed buried in the trough. The bit line is enclosed by a dielectric material. A strap is formed extending through the dielectric material to connect the bit line to the semiconductor substrate. The trough is filled with doped glass. The glass is recessed below the nitride layer. A polysilicon layer is formed over the device. The polysilicon has an undoped portion above part of the glass in the trough. The undoped portion of the polysilicon is removed. A portion of the glass is removed using the polysilicon as a mask to form an opening in the trough. The opening is filled with an insulating material. The remaining portion of the glass is removed from the trough. A gate conductor is formed in the area vacated by the glass.
Furthermore, the present invention provides a method of forming a semiconductor device. A buried bit line and a conductive strap are formed in a trough in a semiconductor substrate. A gate conductor is formed in the trough above the buried bit line. Wordline troughs are formed substantially orthogonal to the bit line. The wordline troughs are filled with glass. The glass is removed above a portion of the gate conductor. The gate conductor is etched using the glass as a mask to form an opening. The opening is filled with an insulator. The remaining portions of the glass are removed. A wordline is formed contacting the gate conductor in the wordline trough.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described only the preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.